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general description the max5200?ax5203 serial input, voltage-output,16-bit digital-to-analog converters (dacs) provide monotonic 16-bit output over temperature without any adjustments. the max5200/max5201 operate from a +5v single power supply featuring an internal reference of +2.5v and an internal gain of 2, while the max5202/ max5203 operate from a +3v or +3.3v single power supply featuring an internal reference of +1.5v and an internal gain of 2. the max5200?ax5203 dac output range is typically from 0 to v dd . the max5200?ax5203 feature a hardware reset input( clr ) that, when pulled low, clears the output to zero code 0000 hex (max5201/max5203) or resets the out-put to midscale code 8000 hex (max5200/max5202). the 3-wire serial interface is compatible with spi/qspi/microwire. all devices have a low- power shutdown mode that reduces the supply current consumption to 1?. the max5200?ax5203 are available in a space-sav- ing 10-pin ?ax package and are guaranteed over the extended temperature range (-40? to +105?). refer to the max5204?ax5207 data sheet for external reference versions. applications low-cost vco/vcxo frequency controlindustrial process control high-resolution offset adjustment features ? guaranteed 16-bit monotonic ? internal reference ? 10-pin 5mm ? 3mm ?ax package ? rail-to-rail output amplifier ? single-supply operation +5v (max5200/max5201)+3v, +3.3v (max5202/max5203) ? low power consumption: 0.8ma ? shutdown mode reduces supply current to 1? ? spi/qspi/microwire-compatible 3-wire serialinterface ? power-on-reset sets output to midscale (max5200/max5202)zero scale (max5201/max5203) max5200?ax5203 low-cost, voltage-output, 16-bit dacs with internal reference in ?ax ________________________________________________________________ maxim integrated products 1 1 23 4 5 10 98 7 6 dgndsclk din ldac v dd agnd ref clr max5200 max5203 max top view cs out pin configuration 19-2655; rev 2; 10/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. spi/qspi are trademarks of motorola, inc.microwire is a trademark of national semiconductor corp. ?ax is a registered trademark of maxim integrated products, inc. selector guide appears at end of data sheet. ordering information part temp range pin-package max5200 aeub -40 c to +105 c 10 ?ax max5200beub -40 c to +105 c 10 ?ax max5200acub 0 c to +70 c 10 ?ax max5201 aeub -40 c to +105 c 10 ?ax max5201beub -40 c to +105 c 10 ?ax max5201acub 0 c to +70 c 10 ?ax max5202 aeub -40 c to +105 c 10 ?ax max5202beub -40 c to +105 c 10 ?ax max5202acub 0 c to +70 c 10 ?ax max5203 aeub -40 c to +105 c 10 ?ax max5203beub -40 c to +105 c 10 ?ax max5203acub 0 c to +70 c 10 ?ax downloaded from: http:///
max5200?ax5203 low-cost, voltage-output, 16-bit dacs with internal reference in ?ax 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to agnd, dgnd ...............................................-0.3v to +6v agnd to dgnd.........................................?-0.3v to +0.3v ref, out to agnd.................................?0.3v to (v dd + 0.3v) clr , ldac , sclk, din, cs to dgnd .......-0.3v to (v dd + 0.3v) maximum current into any pin............................................50ma continuous power dissipation (t a = +70?) 10-pin ?ax (derate 5.6mw/? above +70?) ........444.4mw operating temperature ranges max520_cub .....................................................0? to +70? max520_eub .........................................-40? to +105? junction temperature ......................................................+150? storage temperature range .............................-60? to +150? lead temperature (soldering, 10s) .................................+300? electrical characteristics?ax5200/max5201(v dd = +4.75v to +5.25v, f sclk = 10mhz (50% duty cycle), output load = 10k ? in parallel with 250pf, t a = t min to t max , unless other- wise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units static performance (note 1) resolution n 16 bits max520_aeub ?0 ?0 max520_acub ?0 ?0 integral nonlinearity (note 2) inl max520_beub ?0 ?0 lsb max520_a_ub (note 3) ? max520_beub (0? to +105?) (note 3) ? differential nonlinearity(note 2) dnl max520_beub (-40? to 0?) ? lsb offset error inferred from measurement at 1c00 hexand ffff hex ? ?5 mv gain error ge within dac output range (note 4) ?.01 ? %fsr power-supply rejection psr v dd = 5v ?%, midscale input ?.06 ?.5 mv/v dynamic performance dac output range (note 2) 0 to v dd v output-voltage slew rate sr 0.6 v/? output settling time to ?lsb of fs,v step = 0.25 v ref to 0.75 v ref 25 ? output noise dac code = 8400 hex, 10khz 175 nv/ hz dac glitch impulse major carry transition (code 7fff hex tocode 8000 hex) 10 nv ? s digital feedthrough code = 0000 hex; cs = v dd ; ldac = 0; sclk, din = 0 or v dd 10 nv ? s wake-up time from software shutdown to 90% of outputcode = ffff hex, c ref = 0.1? 50 ? power-up time from power applied to 90% of outputcode = ffff hex 10 ms downloaded from: http:///
max5200?ax5203 low-cost, voltage-output, 16-bit dacs with internal reference in ?ax _______________________________________________________________________________________ 3 electrical characteristics?ax5200/max5201 (continued)(v dd = +4.75v to +5.25v, f sclk = 10mhz (50% duty cycle), output load = 10k ? in parallel with 250pf, t a = t min to t max , unless other- wise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units internal reference v ref output voltage t a = +25? 2.48 2.5 2.52 v t a = 0? to +70? ?5 v ref tempco t a = -40? to +105? ?0 ppm/? digital inputs (din, sclk, cs , clr , ldac ) input high voltage v ih 2.4 v input low voltage v il 0.8 v input hysteresis v hyst 200 mv input leakage i in digital inputs = 0 or v dd ? ? input capacitance c in 15 pf power requirements positive power supply v dd 4.75 5.25 v positive supply current i dd all digital inputs at 0 or v dd (note 5) 0.8 1.5 ma shutdown supply current i shdn all digital inputs at 0 or v dd 11 0 a timing characteristics sclk frequency f sclk 10 mhz sclk clock period t cp 100 ns sclk pulse width high t ch 40 ns sclk pulse width low t cl 40 ns din setup time t ds 40 ns din hold time t dh 0n s cs fall to sclk rise setup time t css 40 ns sclk rise to cs rise hold time t csh 0n s sclk rise to cs fall ignore t cs0 10 ns cs rise to sclk rise ignore t cs1 40 ns ldac pulse width t ldac 40 ns cs rise to ldac low setup t ldacs 40 ns sclk fall to cs fall ignore t csol 10 ns cs pulse width low for shutdown t cswl 40 ns cs pulse width high t cswh 100 ns downloaded from: http:///
max5200?ax5203 low-cost, voltage-output, 16-bit dacs with internal reference in ?ax 4 _______________________________________________________________________________________ parameter symbol conditions min typ max units static performance (note 1) resolution n 16 bits max520_aeub ?0 ?0 max520_acub ?0 ?0 integral nonlinearity (note 2) inl max520_beub ?0 ?0 lsb max520_a_ub (note 3) ? max520_beub (0? to +105?) (note 3) ? differential nonlinearity(note 2) dnl max520_beub (-40? to 0?) ? lsb offset error inferred from measurement at 3800 hex andffff hex ? ?5 mv gain error ge within dac output range (note 4) ?.01 ?.0 %fsr power-supply rejection psr v dd = 3v ?0%, midscale input ?.06 ?.5 mv/v dynamic performance dac output range (note 2) 0 to v dd v voltage-output slew rate sr 0.6 v/? output settling time to ? lsb of fs,v step = 0.25 ? v ref to 0.75 ? v ref 25 ? output noise code = 8400 hex, 10khz 175 nv/ hz reference feedthrough code = 0000 hex at 100khz, v ref = 1v p-p 1 mv p-p dac glitch impulse major carry transition (code 7fff hex tocode 8000 hex) 10 nv ? s digital feedthrough code = 0000 hex; cs = v dd ; ldac = 0; sclk, din = 0 or v dd levels 10 nv ? s wake-up time from software shutdown to 90% of outputcode = ffff hex 50 ? power-up time from power applied to 90% of outputcode = ffff hex 10 ms electrical characteristics?ax5202/max5203(v dd = +2.7v to +3.6v, f sclk = 10mhz (50% duty cycle), output load = 10k ? in parallel with 250pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) downloaded from: http:///
max5200?ax5203 low-cost, voltage-output, 16-bit dacs with internal reference in ?ax _______________________________________________________________________________________ 5 parameter symbol conditions min typ max units internal reference v ref output voltage t a = +25? 1.46 1.5 1.54 v t a = 0? to +70? ?5 v ref tempco t a = -40? to +105? ?0 ppm/? digital inputs (din, sclk, cs , clr , ldac ) input high voltage v ih 2.1 v input low voltage v il 0.6 v input hysteresis v hyst 200 mv input leakage i in digital inputs = 0 or v dd ? ? input capacitance c in 15 pf power requirements positive power supply v dd 2.7 3.6 v positive supply current i dd all digital inputs at 0 or v dd (note 5) 0.8 1.5 ma shutdown supply current i shdn all digital inputs at 0 or v dd 11 0 a timing characteristics sclk frequency f sclk 10 mhz sclk clock period t cp 100 ns sclk pulse width high t ch 40 ns sclk pulse width low t cl 40 ns din setup time t ds 40 ns din hold time t dh 0n s cs fall to sclk rise setup time t css 40 ns sclk rise to cs rise hold time t csh 0n s sclk rise to cs fall ignore t cs0 10 ns cs rise to sclk rise ignore t cs1 40 ns ldac pulse width t ldac 40 ns cs rise to ldac low setup t ldacs 40 ns sclk fall to cs fall ignore t csol 10 ns c s p ul se w i d th low for s hutd ow n t cswl 40 ns cs pulse width high t cswh 100 ns note 1: static performance tested at v dd = +5.0v (max5200/max5201) and at v dd = +3.0v (max5202/max5203). note 2: inl and dnl are guaranteed for outputs between 0.5v to (v dd - 0.5v). note 3: guaranteed monotonic. note 4: v ref = 2.5v (max5200/max5201) and v ref = 1.5v (max5202/max5203). note 5: r l = , digital inputs are at v dd or dgnd. electrical characteristics?ax5202/max5203 (continued)(v dd = +2.7v to +3.6v, f sclk = 10mhz (50% duty cycle), output load = 10k ? in parallel with 250pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) downloaded from: http:///
100 10k 100k output noise density vs. frequency max5200 toc07 frequency (hz) voltage noise density (nv/ hz ) 1k 700 0 100 200 300 400 600500 dac code = 8400 hex max5200?ax5203 low-cost, voltage-output, 16-bit dacs with internal reference in ?ax 6 _______________________________________________________________________________________ supply current vs. temperature max5200 toc01 temperature ( c) supply current (ma) 75 50 25 0 -40 -20 0.6 0.7 0.8 0.9 1.00.5 85 integral nonlinearity vs. code max5200 toc02 dac code inl (lsb) 60,000 50,000 10,000 20,000 30,000 40,000 -12 -8 -4 0 4 8 12 16 -16 0 70,000 differential nonlinearity vs. code max5200 toc03 dac code dnl (lsb) -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 -1.00 0 60,000 50,000 10,000 20,000 30,000 40,000 70,000 gain error vs. temperature max5200 toc04 temperature ( c) gain error (%fsr) 60 40 20 0 -20 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.10 -0.10 -40 80 offset error vs. temperature max5200 toc05 temperature ( c) offset error (mv) -0.30 -0.20 -0.10 0 0.10 0.20 0.30 0.40 -0.40 60 40 20 0 -20 -40 80 half-scale output settling time (code from 4000h to c000h) max5200 toc06a 40 s/div out1v/div out1mv/div r load = 10k ? c load = 250pf small signal (1mv/div) large signal (1v/div) half-scale output settling time (code from c000h to 4000h) max5200 toc06b 40 s/div out1v/div out1mv/div r load = 10k ? c load = 250pf small signal (1mv/div) large signal (1v/div) t ypical operating characteristics (v dd = +5v, t a = +25?, unless otherwise noted.) downloaded from: http:///
max5200?ax5203 low-cost, voltage-output, 16-bit dacs with internal reference in ?ax _______________________________________________________________________________________ 7 source-current capability max5200 toc08 source current (ma) output voltage (v) 30 20 10 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 04 0 code = ffff hex code = c000 hex code = 8000 hex sink-current capability max5200 toc09 sink current (ma) output voltage (v) 12 9 6 3 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 01 5 code = 0000 hex code = 4000 hex major-carry output glitch (code from 8000h to 7fffh) max5200 toc10 1 s/div out(ac-coupled, 5mv/div) major-carry output glitch (code from 7fffh to 8000h) max5200 toc11 1 s/div out(ac-coupled, 5mv/div) shutdown current vs. temperature max5200 toc12 temperature ( c) shutdown current ( a) 60 -20 0 20 40 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 -1.00 -40 80 t ypical operating characteristics (continued) (v dd = +5v, t a = +25?, unless otherwise noted.) downloaded from: http:///
max5200?ax5203 low-cost, voltage-output, 16-bit dacs with internal reference in ?ax 8 _______________________________________________________________________________________ detailed description the max5200?ax5203 serial 16-bit, voltage-output dacs are easily configured with a 3-wire serial inter- face. these devices offer full 16-bit performance with less than ?0lsb integral linearity error and less than ?lsb differential linearity error, thus ensuring monoto- nic performance. serial data transfer minimizes the number of package pins required. the max5200 max5203 include control-logic circuitry, a 16-bit data-in shift register, and a dac register. in addition, these devices employ a precision-bandgap reference and trimmed internal resistors to produce a gain of 2v/v, maximizing the output voltage swing. the max5200?ax5203 output is buffered and the full- scale output voltage is 2 ? v ref . the max5200?ax5203 feature a hardware reset input( clr ) that, when pulled low, clears the dac output to zero code 0000h (max5201/max5203) or resets thedac output to midscale code 8000 hex (max5200/ max5202). for normal operation, connect clr to v dd . internal reference the max5200/max5201 (+5v supply) include an inter-nal reference of 2.5v while the max5202/max5203 (+3v supply) include an internal reference of 1.5v. the dac output range is from 0 to 2 ? v ref . do not drive external circuitry from this reference. to improve dacoutput noise performance, bypass with a low leakage 0.1? minimum capacitor to agnd. digital interface the max5200?ax5203 digital interface is a standard3-wire connection compatible with spi/qspi/ microwire and most dsp interfaces. all of the digital input pins ( cs , sclk, din, clr, and ldac ) are ttl compatible. sclk can accept clock frequencies ashigh as 10mhz for a +5v supply and 10mhz for a +3v or +3.3v supply. one of two methods can be used when interfacing and updating the max5200?ax5203. the first requires three digital inputs: cs , din, and sclk (figure 2). the active-low chip-select input ( cs ) enables the serial pin description pin name function 1 clr reset dac active-low input. pull clr low to reset the dac output to midscale output (8000 hex) for max5200/max5202 and to zero-scale output (0000 hex) for max5201/max5203. for normaloperation, connect clr to v dd . 2 ref reference voltage output. provides a +2.5v (max5200/max5201) or +1.5v (max5202/max5203)nominal output. for improved noise performance, bypass with a minimum 0.1? capacitor to agnd. 3 agnd analog ground 4v dd positive supply voltage. bypass v dd to agnd with a 10? capacitor in parallel with a 0.1? capacitor. 5 out dac output voltage 6 cs active-low chip-select input 7 ldac load dac input 8d in serial data input 9 sclk serial clock input. duty cycle must be 40% to 60%. 10 dgnd digital ground clr agnd ref 16-bit dac bandgap ref 16-bit data latch din sclk cs control logic ldac out dgnd v dd max5200 max5203 serial input register figure 1. max5200?ax5203 simplified functional diagram downloaded from: http:///
max5200?ax5203 low-cost, voltage-output, 16-bit dacs with internal reference in ?ax _______________________________________________________________________________________ 9 data loading at the data input (din). pull cs low and clock in each bit of the 16-bit digital word on the risingedge of the serial clock (sclk). two 8-bit bytes can be used, and do not require any additional time between them. pulling cs high after loading the 16-bit word transfers that code into the dac register and thenupdates the output. if cs is not kept low during the entire loading of the 16-bit word, data is corrupted. inthis case, a new 16-bit word must be loaded. ldac must be kept low at all times for the above instructions.an alternate method of interfacing and updating the max5200?ax5203 can be done with a fourth digital input, the active-low load dac ( ldac ). ldac allows the output to update asynchronously after cs goes high. it is useful when updating multiple max5200max5203s synchronously when sharing a single ldac and cs line. ldac must be kept high at all times dur- ing the data-loading sequence and must only beasserted when cs is high. asserting ldac when cs is low can cause corrupted data. to operate themax5200?ax5203 using ldac , pull ldac high, pull cs low, load the 16-bit word as described in the previ- ous paragraph, and pull cs high again. following these commands, the dac output only updates when ldac is asserted low (figure 3). shutdown mode the low-power shutdown mode reduces supply currentto typically 1? and a maximum of 10?. shutdown mode is not activated through command words, as is common among d/a converters. these devices require careful manipulation of cs and sclk (figure 4). shutting down to shut down the max5200?ax5203, change thestate of sclk (either a high to low or low to high transi- tion can be used) and pulse two falling cs edges. in order to keep the device in shutdown mode, sclkmust not change state. sclk must remain in the state it is in after the two cs pulses. waking up there are two methods to wake up the max5200max5203. pulse one falling cs edge or transition sclk. it takes 50? typically from the cs falling edge or sclk transition for the dac to return to normal operation. power-on reset the max5200?ax5203 have a power-on reset circuit toset the dac? output to a known state when v dd is first applied. the max5200/max5202 reset to midscale (code8000 hex) upon power-up. the max5201/max5203 reset to zero scale (code 0000 hex) upon power-up. this ensures that unwanted output voltages do not occur immediately following a system power-up, such as a loss of power. it is required to apply v dd first before any other inputs (din, sclk, clr , ldac , and cs ). t cl t ch t css d14 d15 t ds t dh d0 t csh t cs1 t cs0 sclk cs din t cp t cswh note: ldac is logic low. figure 2. 3-wire interface timing diagram downloaded from: http:///
max5200?ax5203 low-cost, voltage-output, 16-bit dacs with internal reference in ?ax 10 ______________________________________________________________________________________ applications information power-supply and bypassing considerations bypass the power supply with a 10? capacitor in par-allel with a 0.1? capacitor to agnd. minimize lead lengths to reduce lead inductance. if noise becomes an issue, use shielding and/or ferrite beads to increase isolation. output buffer the max5200max5203 include low-offset, low-noise buffers enabling the output to source 15ma or sink 5ma. the output buffer operates at a slew rate of 0.6v/?. with a 1/4 fs to 3/4 fs output transition, the buffer output typically settles to 1 lsb in less than 25?. the max5200max5203 output buffers provide a low 0.2 ? typical output impedance. the max5200 max5203 buffer amplifiers typically produce175nv/ hz noise at 10khz. t cs0l t cswl t cswh shutdown wake-up t cs0l t cswl t cswh shutdown wake-up sclk cs a. waking up using a third falling edge on cs. b. waking up using a transition on sclk. sclk cs figure 4. shutdown timing t cl t ch t css d14 d15 t ds t dh d0 t csh t cs1 t cs0 sclk cs din ldac t cp t cswh t ldacs t ldac figure 3. 4-wire interface timing diagram downloaded from: http:///
max5200?ax5203 low-cost, voltage-output, 16-bit dacs with internal reference in ?ax ______________________________________________________________________________________ 11 bipolar configuration the max5200?ax5203 are designed for unipolar opera-tion, but can be used in bipolar applications with an exter- nal amplifier and resistors. figure 5 shows the max5200?ax5203 configured for bipolar operation. the op amp is set for unity gain. table 1 lists the offset binary code for this circuit. the output voltage range is ? ref . layout considerations digital and ac transient signals coupling to agnd cancreate noise at the output. connect agnd to the high- est quality ground available. use proper grounding techniques, such as a multilayer board with a low- inductance ground plane. wire-wrapped boards and sockets are not recommended. for optimum system performance, use printed circuit (pc) boards with sep- arate analog and digital ground planes. connect the two ground planes together at the low-impedance power-supply source. connect dgnd and agnd pins together at the ic. the best ground connection is achieved by connecting the dac? dgnd and agnd together, and then connecting that point to the system analog ground plane. if the dac? dgnd is connected to the system digital ground, digital noise can get through the dac? analog portion. chip information transistor count: 8764process: bicmos clr agnd v dd ref dinsclk cs dgnd bipolar out ( v ref ) ldac out mc68xxxx 10 f 0.1 f pcs0 mosi sclk +5v -5v max5200 max5203 max400 figure 5. max5200?ax5203 typical operating circuit?ipolar output dac latch contents msb lsb analog output, v out 1111 1111 1111 1111 +v ref (32,767 / 32,768) 1000 0000 0000 0001 +v ref (1 / 32,768) 1000 0000 0000 0000 0v 0111 1111 1111 1111 -v ref (1 / 32,768) 0000 0000 0000 0000 -v ref (32,768 / 32,768) table 1. bipolar code table downloaded from: http:///
max5200?ax5203 low-cost, voltage-output, 16-bit dacs with internal reference in ?ax 12 ______________________________________________________________________________________ selector guide part integral nonlinearity (lsb, max) supply voltage range (v) reference input range (v) power-on-reset value max5200aeub 20 4.75 to 5.25 2.5 midscale max5200acub 20 4.75 to 5.25 2.5 midscale max5200beub 40 4.75 to 5.25 2.5 midscale max5201aeub 20 4.75 to 5.25 2.5 zero max5201acub 20 4.75 to 5.25 2.5 zero max5201beub 40 4.75 to 5.25 2.5 zero max5202aeub 20 2.7 to 3.6 1.5 midscale max5202acub 20 2.7 to 3.6 1.5 midscale max5202beub 40 2.7 to 3.6 1.5 midscale max5203aeub 20 2.7 to 3.6 1.5 zero max5203acub 20 2.7 to 3.6 1.5 zero max5203beub 40 2.7 to 3.6 1.5 zero downloaded from: http:///
max5200?ax5203 low-cost, voltage-output, 16-bit dacs with internal reference in ?ax maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 13 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/packages .) 10lumax.eps package outline, 10l umax/usop 1 1 21-0061 i rev. document control no. approval proprietary information title: top view front view 1 0.498 ref 0.0196 ref s 6 side view bottom view 0 0 6 0.037 ref 0.0078 max 0.006 0.043 0.118 0.120 0.199 0.0275 0.118 0.0106 0.120 0.0197 bsc inches 1 10 l1 0.0035 0.007 e c b 0.187 0.0157 0.114 h l e2 dim 0.116 0.114 0.116 0.002 d2 e1 a1 d1 min - a 0.940 ref 0.500 bsc 0.090 0.177 4.75 2.89 0.40 0.200 0.270 5.05 0.70 3.00 millimeters 0.05 2.89 2.95 2.95 - min 3.00 3.05 0.15 3.05 max 1.10 10 0.60.1 0.60.1 00.500.1 h 4x s e d2 d1 b a2 a e2 e1 l l1 c gage plane a2 0.030 0.037 0.75 0.95 a1 downloaded from: http:///

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